1. Field of the Invention
The present invention relates to a method for reducing the number of wire-bond loop heights which are required in comparison with a total quantity of power and signal rings employed in low profile wire-bond integrated circuit packages. Moreover, the invention is further directed to the provision of low profile wire-bond packages which are produced in accordance with the method pursuant to the invention.
Generally, low profile wire-bond integrated circuit or printed circuit wire-bond packages are intended to be designed so as to meet standards which have been set by the JEDEC (Industry Society Joint Electron Device Engineering Council) defining low-profile design outlines specifying package height restrictions, such as the height to which a wire-bond wire may extend or loop above a package substrate. This particular height limitation in the formation of the wire loops is normally imposed either through the assembled distance between the laminate of the substrate and the mounting card or chip (cavity parts) or the encapsulation mold fixture and the laminate (for chip-up package parts). Basically, these industry standards defining the height limitations of wire-bond wire loops are applicable to both the so-called cavity-down plastic ball grid arrays (PBGA) or chip-up packages.
Ordinarily, each different wire-bond wire length extending in a horizontal direction, when employed in a low-profile wire-bond package and forming a vertically rising wire loop, must be separated so as to be adequately spaced in its vertical extent or orientation from other wire-bond wire loops or lengths of the package in order to prevent the occurrence of possible electrical shorts and other potential damage which can be readily encountered during the assembly of the wire-bond package, and attempts to avoid such difficulties may result in the exceeding of maximum allowable encapsulation package heights depending upon the number of wire loop heights employed.
For instance, an integrated circuit chip with a single row of wire-bond pads which is wired to a substrate with a ground ring, voltage ring and signal ring may result in three loops, each increasing in loop height as defined by the wires of the formed package. In the event that the chip pads are staggered, such as through the use of two voltage, one ground and two signal rings, this may provide for a total of five increasing loop heights. Consequently, by way of example, if each loop is separated by a distance or vertical spacing of 75 microns, the resulting vertical height of the upper-most wire for a three loop wire-bond structure would potentially measure 225 microns; whereas, for a five-loop structure this overall vertical wire loop height may measure up to 375 microns. Thus, an addition of the thickness of an encapsulant over the wire loops, can be an increase of an additional height of 200 microns of material above the package substrate, resulting in a total height of approximately 425 microns for a three wire-loop arrangement, and of up to 575 microns for a five wire-loop package design.
However, pursuant to current JEDEC industry standards specifying the limits of encapsulation height measured from the module for cavity down parts of wire-bond packages are set to 470 microns for a 1.27 mm grid, and 381 microns for a 1 mm grid. Consequently, although the wire bonds may fit within the maximum specified package height limits, current assembling installations are unable to produce the package modules, inasmuch as the distance between the highest loop and the top or surface of the encapsulant may be too short to provide a satisfactory package construction.
Thus, a typical diameter for a solder ball (prior to reflow) utilized on a so-called cavity-down plastic ball grid array (PBGA) with a 1.27 mm grid is normally approximately 600 microns, and 500 microns for a 1 mm grid. However, production tolerances which are encountered during assembly must be accommodated within a 120 to 130 micron range in order to be able to properly connect the solder balls to the card or substrate employing the maximum specified encapsulation height as set forth hereinabove in compliance with the industry standards.
2. Discussion of the Prior Art
At this time, industry manufacturing practices which are intended to solve the problem of managing constraints in the overall height of the plurality of encapsulated wire-bond loops in forming the low-profile wire-bond integrated circuit packages, are equally applicable to cavity-down ball grid array (BGA) and chip-up packages, such as but not limited to land grid arrays (LGAs) designed to JEDEC low profile outline standards, whereby package height restrictions necessitate wire loop heights and encapsulating thicknesses to be produced to closer dimensions, thereby resulting in possible yield or output losses. The yield losses are encountered, inasmuch as the wires are not spaced apart to an adequate extent relative to each other so as to prevent shorting of potentially at least some wires during encapsulation thereof. This is essentially an unacceptable limitation in the manufacture of low-profile wire bond packages. Further problems are encountered which would render the arrangements unacceptable and unworkable in nature when confronted with smaller diameter solder balls utilized for JEDEC standard BGA pitches of 1 mm and less, which further reduces any space or height available from the printed circuit board to the encapsulant.